1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a ferroelectric memory device and a method of fabricating the same.
2. Description of the Related Art
A ferroelectric memory device uses a ferroelectric material such as PZT Pb(ZrxTi1x)O3 or BST (BaSrTiO3) as a capacitor dielectric layer. The ferroelectric substance has a remnant polarization characteristic (Pr) different from a conventional dielectric substance such as oxide, silicon nitride and tantalum pentoxide. Thus, polarization is maintained even when external power is cut off and, as a result, data are retained.
Remnant polarization may be degraded during ferroelectric memory device fabrication e, g, the interconnection formation after the formation of a ferroelectric capacitor. When the interconnection is formed of a metal layer reflowed by heat treatment after deposition, the remnant polarization can be degraded by stress applied to the capacitor resulting from metal expansion. Forming the metal interconnection without reflow by thermal treatment reduces the stress and prevents degradation.
FIG. 1 is a hysteresis graph of a ferroelectric capacitor with respect to an interconnection process. The horizontal, or x-axis, shows the voltage applied to the capacitor and the vertical, or y-axis, indicates polarization per unit area of the capacitor. Line 1 is a hysteresis curve of a ferroelectric capacitor and illustrates case 1, in which the interconnection is formed of sputter-deposited aluminum, and line 2 is another hysteresis curve and illustrates case 2, in which the capacitor is made from aluminum reflowed by thermal treatment for 60 seconds at a temperature of 550° C. after deposition.
As illustrated, case 1 has higher polarization than case 2. Even after cutting off power, the remnant polarization of case 1 is higher than that of case 2. However, when a ferroelectric memory device is fabricated using the conventional method, the sputter-deposited metal interconnection is problematic.
FIGS. 2 through 5 illustrate cross-sectional views showing a conventional method of fabricating a ferroelectric memory device.
FIG. 2 illustrates a semiconductor substrate 100 with a cell array region, ‘a,’ having a cell transistor and a peripheral circuit region, ‘b,’ having a peripheral circuit transistor. A bit line pad 112 and a storage node contact pad 114 are connected to a cell source 106 and a cell drain 104, respectively. Then, a first interlayer dielectric layer 116 is formed over the surface of the resulting structure where the bit line pad 112 and the storage node contact pad 114 are formed. A bit line 124 is connected to the bit line pad 112 through the first interlayer dielectric layer 116. Concurrently, a source/drain contact pad 126 and a gate contact pad 128 are respectively connected to a source/drain 110 and a gate electrode 108 of the peripheral circuit transistor through the first interlayer dielectric layer 116.
FIG. 3 shows the formation of a second interlayer dielectric layer 130 over the surface of the resulting structure. A storage node contact plug 138 is connected to the storage node contact pad 114 through the first and second interlayer dielectric layers 116, 130. A ferroelectric capacitor 150 is then connected to the storage node contact plug 138 on the second interlayer dielectric layer 130, and a third interlayer dielectric layer 152 is formed over the surface of the substrate where the storage node contact plug 138 is formed. The second and third interlayer dielectric layers 130, 152 are sequentially patterned to form first via holes 136 exposing the source/drain contact pad 126 and the gate contact pad 128.
Referring to FIG. 4 a first conductive layer is formed over the surface of the resulting structure. As described above, the first conductive layer is formed of a sputter-deposited metal layer so as not to degrade the capacitor dielectric layer. The first conductive layer is then patterned to form a first interconnection 156 selectively connected to the source/drain node contact pad 126 and the gate contact pad 128.
The first via hole 136 has a high aspect ratio because it exposes the source/drain contact pad 126 and the gate contact pad 128 through the second and third interlayer dielectric layers 130, 152. Because of the high aspect ratio, metal layer is improperly deposited on the sidewalls of the via hole 136 and thus the first interconnection 156 is cut off or not uniformly formed as indicated at 157, thereby increasing resistance. If the first conductive layer is formed of the sputter-deposited metal layer, the problem worsens.
FIG. 5 shows a fourth interlayer dielectric layer 158 formed over the surface of the resulting structure where the first interconnection 156 is formed. The third and fourth interlayer dielectric layers 152, 158 are sequentially patterned to form a plate electrode hole 160 exposing the ferroelectric capacitor 150 and forming a second via hole 162 exposing the first interconnection 156. Next, a second conductive layer is formed over the surface of the fourth interlayer dielectric layer 158. Like the first conductive layer, the second conductive layer may be formed of a sputter-deposited metal to prevent the degradation of the ferroelectric capacitor 150. The second conductive layer is then patterned to form a plate electrode line 164 connected to the ferroelectric capacitor 150 and concurrently forms a second interconnection 166 connected to the first interconnection 156. The plate electrode line 164 and the second interconnection 166 may be selectively connected to a desired region of the semiconductor substrate-100.
As described above, in order to prevent degrading the polarization of the ferroelectric capacitor, the interconnection may be formed of sputter-deposited aluminum. However, because the metal interconnection of a conventional ferroelectric device fills the sidewalls of the high aspect ratio via hole and is connected to a gate electrode and a source/drain of the peripheral circuit, when the interconnection is formed of the sputter-deposited metal the high aspect ratio causes the metal layer to be improperly deposited on the sidewalls of the via hole. Thus, the metal interconnection is cut off and resistance is increased, degrading reliability of the metal interconnection.